General profile
With the development of electronic products to light, thin and small, PCBs are also pushed into high density, high difficulty. Among them, via in pad is one of the topics that engineering designer can not avoid. It is a main part of multilayer PCBs and directly helps to save PCB real estate up to 50% for fine pitch BGA and flip chip components.The main difficulty for VIP is the via-plug process, ie how to prevent soldering tin from into via or solder mask onto pads.
Solutions
Via in pad hole circuit board technology will solve the high-density packaging laminated hole processing.
Applications
1) Through hole,BGA package on multilayer PCBs -->via on ball -->resin via plug -->ground surface -->copper electroplated on plugged via.
2) Blind via, a technique similar to a through hole, with a controlled depth of 0.075mm for the blind hole.
3) HDI multi-step stacking hole technology.The interconnected processing technology is very complex. Multiple hole filling and multiple copper pressing are used to complete the manufacturing process.Such structure in medical, communication products are widely recommended for application.
Design For Manufacture
This manufacturability guide provides an overview of various areas that printed circuit board designer may take into consideration on the fabrication possibility, manufacturing cost and reliability of their products. This DFM is divided into 6 parts for our readers. This is the section II.
| Serial NO. |
Procedure |
Item |
Manufacturing capability |
| Large volume (S<100 m²) |
Middle volume (S<10 m²) |
Prototype(S<1m²) |
|
| 14 |
Laminating |
Tolerance of laminate thickness |
±10% PCB thick |
±10% PCB thick |
±8% PCB thick |
| 15 |
Maximum laminate thickness |
4.0mm |
6.0mm |
7.0mm |
| 16 |
Laminate alignment accuracy |
≤±5 mil |
≤±4 mil |
≤±4 mil |
| 17 |
Drill (18um, 35um, 70um etc are finished copper. If not mentioned copper, finished 1oz is the default value ) |
Min.drill bit diameter |
0.2 mm |
0.2 mm |
0.2 mm |
| 18 |
Min.slot router diameter |
0.60 mm |
0.60 mm |
0.60 mm |
| 19 |
Min.tolerance of PTH slots |
±0.15mm |
±0.15mm |
±0.1mm |
| 20 |
Max.aspect ratio |
1:08 |
1:12 |
1:12 |
| 21 |
Hole tolerance |
±3mil |
±3mil |
±3mil |
| 22 |
Space of via to via |
6mil(same net),12mil(different net) |
6mil(same net),14mil(different net) |
4mil(same net),12mil(different net) |
| 23 |
Space of component hole to component hole |
12mil(same net),16mil(different net) |
12mil(same net),16mil(different net) |
10mil(same net),14mil(different net) |
| 24 |
Etching |
Min.width of etching logo |
10mil(18um),12 mil (35um),12 mil(70um) |
8mil(18um),10mil(35um),12 mil(70um) |
6mil(18um),8 mil(35um),12mil(70um) |
| 25 |
Etch factor |
1.6-2.2 |
1.6-2.2 |
1.6-2.2 |
| 26 |
Outer layer(18um, 35um, 70um etc are finished copper. If not mentioned copper, finished 1oz is the default value ) |
Min.via pad diameter |
20mil |
16mil |
16mil |
| 27 |
Min.BGA pad diameter |
12mil |
12mil |
10mil |
| 28 |
Min.track and spacing |
5/5mil(18um) |
4/4mil(18um) |
3/3.5mil(18um) |
| 5/5mil(35um) |
4/4mil(35um) |
3/4mil(35um) |
| 7/9mil(70um) |
6/8mil(70um) |
6/7mil(70um) |
| 9/11mil(105um) |
8/10mil(105um) |
8/9mil(105um) |
| 13/13mil(140um) |
12/12mil(140um) |
12/11mil(140um) |
| 29 |
Minimum grid |
10/10mil(35um) |
8/8mil(35um) |
4/8mil(35um) |
| 30 |
Min.space (conductor to pad, pad to pad) |
6mil(18um) |
5mil(18um) |
4mil(18um) |
| 6mil(35um) |
5mil(35um) |
4mil(35um) |
| 9mil(70um) |
8mil(70um) |
7mil(70um) |
| 11mil(105um) |
10mil(105um) |
9mil(105um) |
| 13mil(140um) |
12mil(140um) |
11mil(140um) |
Audited Supplier 
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